The invention is in the field of semiconductor technology and relates to a method for fabricating a microelectronic structure having the following steps: providing a semiconductor substrate having a main area and at least one trench disposed at the main area, the trench having at least one side wall and the side wall and the main area having at least one common edge region; filling the trench with an insulating material leaving the edge region uncovered; and oxidizing the main area and the edge region to form an oxide layer having a thickness in the edge region at least just as great as at the main area.
During the fabrication of integrated circuits, active components disposed in the semiconductor substrate have to be suitably insulated from one another. One possibility for doing that resides in insulating the active components from one another through the use of trench isolation (so-called Shallow Trench Isolation (STI)). In that type of insulation, trenches are etched into the semiconductor substrate and subsequently filled with an insulating material.
Instances of such trench isolation can be found, for example, in German Published, Non-Prosecuted Patent Application DE 197 31 203 A1 and German Patent DE 195 35 629 C1. In the methods described therein, an oxide layer serving as gate oxide and a polysilicon layer serving as gate electrode are applied to the semiconductor substrate. Afterwards, trenches are etched into that layer system down into the semiconductor substrate. The trenches define the position of the individual active components. Finally, the trenches are filled with a thermal oxide. In those methods, however, it has turned out to be problematic that in the course of filling the trenches, the semiconductor substrate and the polysilicon may be partially oxidized, thereby producing a gate dielectric having a varying thickness. In order to minimize that problem, German Patent DE 197 31 203 C1 proposes implanting nitrogen into the gate dielectric after the formation of the gate oxide and before the filling of the trenches, in order to thereby limit the lateral oxygen diffusion. It has been shown, however, that such a measure also cannot completely eliminate the problem.
U.S. Pat. No. 5,882,993 discloses the use of nitrogen for forming gate dielectrics of varying thicknesses. To that end, nitrogen is implanted in a laterally varying concentration into a silicon substrate provided with trenches that have already been filled, and an oxide is subsequently formed thereon. However, due to the varying nitrogen concentration in the silicon substrate, oxides of varying thicknesses are formed which may often have an inhomogeneous thickness in the transition regions to the trenches that have already been filled.
It is problematic, moreover, that gate oxides are often severely thinned at the transition regions from the silicon substrate to the isolation trenches (e.g. so-called Shallow Trench Isolation). So-called corner devices form at the transition regions. The corner devices usually have a lower threshold voltage than the actual transistor and, as a result, adversely affect the switching characteristic and the leakage current behavior of the entire transistor. That behavior is additionally aggravated by a thin gate oxide at the transition regions. The effect of the corner device has usually been reduced through the use of a higher channel doping, but that in turn entails undesirable side effects.
In order to avoid the corner device, International Publication No. WO 99/25018 attempts to damage the edge region between the main area and the trench by amorphizing implantation. The aim is to produce a somewhat thicker oxide layer there in the course of the subsequent oxidation.
The method mentioned in the introduction, on the other hand, is disclosed e.g. in U.S. Pat. No. 5,891,787, where, after the formation and filling of a trench, silicon is implanted into the edge regions between the trench and the main area. That implantation is intended to bring about an excess of silicon atoms in the edge region with the main area covered, so that a thicker oxide layer than in the region of the main area can be produced there in the course of the subsequent oxidation. The implantation of nitrogen for the formation of diffusion barrier centers and elimination of crystal defects is described as an alternative. Although local thickening of the oxide layer serving as gate dielectric can be achieved by that method, microelectronic structures that are fabricated in that way only exhibit unsatisfactory properties. That is due, for example, to the fact that the oxide layer produced due to the silicon excess has a different material structure than that formed on the main area and exhibits an increased leakage current tendency. The formation of the corner device is thereby likewise only suppressed to an insufficient extent.
It is accordingly an object of the invention to provide a method for fabricating a microelectronic structure, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and which enables largely homogeneous gate dielectrics to be formed, with the formation of a corner device being suppressed.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a microelectronic structure, which comprises the following steps providing a semiconductor substrate having a main area and at least one trench disposed at the main area, the at least one trench having at least one side wall, and the at least one side wall and the main area having at least one common edge region; filling the trench with an insulating material leaving the edge region uncovered; introducing nitrogen into the semiconductor substrate to provide a higher nitrogen concentration in the vicinity of the main area than in the edge region; and then oxidizing the main area and the edge region to form an oxide layer with a thickness in the edge region at least just as great as on the main area, the nitrogen causing the oxide layer to grow more slowly in the main area than in the edge region.
According to the present invention, a semiconductor substrate is provided and at least one trench having a side wall is introduced at the main area of the semiconductor substrate. This trench defines, for example, the position of an active component in the semiconductor substrate. In the transition region between the side wall of the trench and the main area of the semiconductor substrate there is an edge region formed by both of them.
Nitrogen is subsequently introduced into the semiconductor substrate, with a higher nitrogen concentration being sought in the region of the main area than in the edge region. In this case, the difference in nitrogen concentration should be dimensioned in such a way that oxide layers each having a predetermined thickness are produced in the course of subsequent oxidation of the semiconductor substrate, i.e. of the main area and of the edge region. In the common edge region between the main area and the side wall, the nitrogen concentration preferably uniformly decreases in the direction of the side wall. The effect that is intended to be achieved as a result of this is that the oxide layer which is subsequently to be formed has an increasing thickness in the edge region and thereby contributes to a uniform transition from the oxide layer thickness on the main area to the oxide layer thickness on the side wall. In this case, however, what is sought is an oxide layer thickness that is as uniform as possible as far as the edge region and even into the edge region.
The particular effect achieved through the use of the method according to the invention is that the oxide layer is not thinned in a disturbing manner in the edge region between the main area and the side wall, and the undesirable influence on the transistor properties by the so-called corner device is thereby avoided. The effect of the corner device is disturbing particularly in the case of a cell transistor required for DRAM cells since, due to increased leakage currents, the stored charge flows away undesirably faster and the memory cell thus has to be refreshed again in shorter time intervals.
A further advantage of the use of the method according to the invention resides in the fact that the lower threshold voltage of the corner device in comparison with the cell transistor (the threshold voltage is lower even given an identical oxide thickness of the corner device and of the cell transistor), can be compensated for by a thicker gate oxide in the edge region.
It has been shown that by targeted retardation of the oxidation of the main area by the nitrogen introduced beforehand, a relatively uniform oxide layer having a sufficient thickness in the edge region can be formed.
Nitrogen is preferably introduced by implantation into the semiconductor substrate, in which case it has proved favorable for nitrogen to be implanted essentially only at the main area and partially in the edge region. This can be achieved, for example, by nitrogen being introduced into the semiconductor substrate by implantation which is to the greatest possible extent perpendicular to the main area. However, the implantation angle relative to the main area may also encompass a certain solid angle range in order to ensure sufficient implantation of nitrogen in the edge region as well.
The implantation of nitrogen should preferably be performed very near the surface, and this can be achieved, for example, by an implantation energy of 10-30 keV. By virtue of the largely perpendicular implantation near the surface, it is possible to establish e.g. a ratio of the nitrogen concentration at the main area to that at the edge region of, preferably, greater than 2 to 1, which manifests itself in a distinctly varying oxide thickness.
A further advantage of the method according to the invention resides in the fact that, due to the compensated threshold voltage of the corner device, it is possible to dispense with a higher doping of the semiconductor substrate. The relatively high doping of the semiconductor substrate is generally used to counteract the decreased threshold voltage of the corner device. However, this high doping, which may be present, for example, in the form of a well doping, unfavorably induces a further leakage mechanism. The latter is referred to as so-called xe2x80x9cjunction leakagexe2x80x9d and manifests itself in a defect-driven and field-driven leakage current in the space charge zone of the PN junction between a source or drain region and the semiconductor substrate. This type of leakage current is predominant particularly in MOSFET transistors having a small channel width.
The relatively high doping of the well, i.e. of the channel region, that is usually necessary can therefore be dispensed with when the method according to the invention is used. As a result, reliable transistors can thus be fabricated which are distinguished, in particular, by a lower leakage current rate and a more accurately defined threshold voltage.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a microelectronic structure, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.